If you have an Embedded Coder license, you can automatically generate embedded C code from the software interface model, build it, and run the executable on Linux on the ARM processor. It includes all the blocks outside of the HDL subsystem, and replaces the HDL subsystem with AXI driver blocks. The software interface model contains the part of your design that runs in software. In the HDL Workflow Advisor, after you generate the IP core, You can create a vivado project in step 4.1, you can optionally generate a software interface model in the Embedded System Integration > Generate Software Interface Model task. Next, you will generate C code to run on the ARM processor to control the LED blink frequency and direction. Click Run This Task to run the Set Target Device and Synthesis Tool task. In the Support Package Installer, select Xilinx Zynq Platform and follow the instructions provided by the Support Package Installer to complete the installation.ġ.4. If you don't have this option, select Get more to open the Support Package Installer. For Target platform, select Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. In the Set Target > Set Target Device and Synthesis Tool task, for Target workflow, select IP Core Generation.ġ.3. Open the HDL Workflow Advisor from the hdlcoder_led_blinking/led_counter subsystem by right-clicking the led_counter subsystem, and choosing HDL Code > HDL Workflow Advisor.ġ.2. Start the IP core generation workflow.ġ.1. You can then integrate the generated IP core with a larger FPGA embedded design in the Xilinx Vivado environment.ġ. HDL Coder packages all the generated files into an IP core folder. HDL Coder generates HDL code from the Simulink blocks, and also generates HDL code for the AXI interface logic connecting the IP core to the embedded processor. The generated IP core is designed to be connected to an embedded processor on an FPGA device. Using the IP Core Generation workflow in the HDL Workflow Advisor enables you to automatically generate a sharable and reusable IP core module from a Simulink model. Generate an HDL IP core using the HDL Workflow Advisor The output port, Read_Back, can be used to read data back to the processor. The output port of the hardware subsystem, LED, connects to the LED hardware. In the embedded software, this means the ARM processor controls the generated IP core by writing to the AXI interface accessible registers. In Simulink, you can use the Slider Gain or Manual Switch block to adjust the input values of the hardware subsystem. All the blocks outside of the subsystem led_counter are used for software implementation. Two input ports, Blink_frequency and Blink_direction, are control ports that determine the LED blink frequency and direction. It models a counter that blinks the LEDs on an FPGA board. In this example, the subsystem led_counter is the hardware subsystem. All the blocks inside this subsystem will be implemented on programmable logic, and all the blocks outside this subsystem will run on the ARM processor. This Atomic Subsystem is the boundary of your hardware-software partition. Group all the blocks you want to implement on programmable logic into an Atomic Subsystem. The first step of the Zynq hardware-software co-design workflow is to decide which parts of your design to implement on the programmable logic, and which parts to run on the ARM processor. Hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2019.1\bin\vivado.bat') Partition your design for hardware and software implementation In this workflow, you perform the following steps: Using the guided workflow shown in this example, you automatically generate HDL code for the programmable logic using HDL Coder, generate C code for the ARM processor using Embedded Coder, and implement the design on the Xilinx Zynq UltraScale+ MPSoC Platform. You can then prepare your design for hardware and software implementation on the Xilinx Zynq UltraScale+ MPSoC by deciding which system elements will be performed by the programmable logic, and which system elements will run on the ARM Cortex-A53. You can use MATLAB® and Simulink® to design, simulate, and verify your application, perform what-if scenarios with algorithms, and optimize parameters. This example is a step-by-step guide that helps you use the HDL Coder™ software to generate a custom HDL IP core which blinks LEDs on the Xilinx Zynq UltraScale+ MPSoC ZCU102 evaluation kit, and shows how to use Embedded Coder® to generate C code that runs on the ARM® processor to control the LED blink frequency.
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